The present invention relates to a semiconductor device, and more particularly to an arrangement of a plurality of pads formed on a semiconductor chip included in a semiconductor device.
A semiconductor chip included in a semiconductor device has a plurality of pads, which are connected to external terminals. During a manufacturing process of the semiconductor chip, a probe needle of a test device for an electric test (pellet-on-wafer (P/W) test) is pressed against some of those pads.
A related semiconductor device is disclosed in JP-A 11-87441 (Patent Literature 1). When a probe needle is pressed against a pad for probing, a surface of the pad is scarred by the needle, making it difficult or uncertain to connect a bonding wire to that pad (bonding). In order to avoid such a situation, the related semiconductor device is configured such that a pad used for an electric test, which is hereinafter referred to as a dual-function pad, has a probe needle area against which a probe needle is pressed and a bonding wire area to which a bonding wire is connected. In other words, the dual-function pad is formed so as to have a larger area (larger pad area) as compared to a pad that is used for bonding but is not used for an electric test, which is hereinafter referred to as a dedicated pad.